1. Field of the Invention
The present invention relates to a phase locked loop (PLL), and in particular to a phase locked loop using a gear shifting algorithm.
2. Description of the Background Art
In general, a clock signal generating circuit provides a high-speed memory chip with an internal clock signal generated by delaying an external clock signal for a predetermined time. However, as a semiconductor memory device has been developed, the memory chips are operated at a higher speed, and there are limitations to delay the external clock signal. Accordingly, a high-performance integrated circuit commonly employs a phase locked loop (PLL) or delay locked loop (DLL) in order to obtain the internal clock signal.
FIG. 1 is a block diagram illustrating a conventional phase locked loop (PLL). In FIG. 1, the conventional PLL includes a phase detector 10, a charge pump 11, a loop filter 12 and a voltage controlled oscillator (VCO) 13.
The phase detector 10 detects a phase difference between the external clock signal CLKX and the feedback internal clock signal CLKI, and is embodied as an exclusive OR gate XOR and JK flip-flop. The charge pump 11 carries out a pumping operation according to phase difference signals UP, DN outputted from the phase detector 10. The loop filter 12 filters an output signal from the charge pump 11, and outputs a control voltage CV to the VCO 13.
The operation of the conventional analog PLL will now be described.
The phase detector 10 compares the phases of the two clock signals CLKX, CLKI, and outputs the phase difference signal DN when the phase of the internal clock signal CLKI is faster than that of the external clock signal CLKX, and outputs the phase difference signal UP when the phase of the internal clock signal CLKI is slower than that of the external clock signal CLKX. The charge pump 11 performs a pumping operation according to the phase difference signal DN or UP outputted from the phase detector 10. The loop filter 12 filters the output signal from the charge pump 1, and outputs a control voltage CV to control an output frequency of the VCO 13.
The VCO 13 controls a frequency of the internal clock signal CLKI according to the control voltage CV, and the internal clock signal CLKI with its frequency controlled is fed back to the phase detector 10. Thus, the conventional PLL repeatedly carries out the above-described operation until the internal clock signal CLKI and the external clock signal CLKX have an identical phase (until locked). When the internal clock signal CLKI is locked to the external clock signal CLKX, the locked internal clock signal CLKI is used as a clock signal for the timing restoration of the integrated circuit, namely the internal circuit.
In general, the PLL must have properties such as a short locking time and a low jitter. However, in the conventional PLL, it takes a remarkably long time to generate the locked internal clock signal CLKI. There is another disadvantage of the conventional PLL in that the jitter is more generated due to the phase difference between the external clock signal CLKX and the internal clock signal CLKI.